VLSI Information Processing Systems (ViPS) Research Group

The VLSI Information Processing Systems (ViPS) Research Group at the University of Illinois led by Prof. Naresh R. Shanbhag focuses on the design of integrated circuits and systems for signal processing and communications. Our work encompasses communication system design, VLSI architectures, and integrated circuit design. Research topics of interest are:

• Communication IC Design: Research in this area focuses on the design of low-power, high-performance VLSI architectures and integrated circuit implementations of broadband communication systems. These projects are heavily influenced by next generation communication standards. 

• Communications-Inspired IC Design: The focus of this area of research is to exploit the wealth of results from the area of communication systems to design reliable and efficient systems-on-a-chip (SOC). In particular, SOCs are viewed as communication networks subject to numerous non-idealities inherent in modern nanometer process technologies such as noise, leakage, process variations, and soft errors. Techniques such as detection, estimation, equalization and coding are employed to combat circuit and device level non-idealities for various SOC sub-systems including computation (datapath, arithmetic units, filters etc.), communication (busses and point-to-point links), and storage (memory).

• Fundamental Bounds on Integrated Circuits: Research activities focus on determining achievable  bounds on energy-efficiency and throughput of nanometer ICs in the presence of non-idealities such as noise, leakage and process variations. Information Theory is employed to obtain efficiency bounds by viewing nanometer ICs as noisy communication networks.

Faculty collaborators: Douglas Jones, Andrew Singer and Rakesh Kumar.

Robust and Energy-Efficient High-Speed Links: The primary goal of our research is to develop a system-aware approach to mixed-signal implementations of high-speed (multi-gigabit) links. System-aware mixed signal design seeks to relax the specifications on the analog and digital circuit blocks thereby facilitating the scaling into nanoscale regimes. We are exploring and exploiting the capability of DSP in conjunction with ECC to reduce power in ADC-based high-speed links for applications in back-plane, I/O, and optical. I/O link specific ECC is being explored in terms of BER performance, latency, encoder and decoder architectures. We are exploring techniques to determine BER-optimal rather than SFDR optimal ADC parameters, and dispersion-tolerant clock-recovery techniques. We will employ ultra low-power DSP techniques based on error-resiliency such as algorithmic noise-tolerance (ANT) on the DSP blocks in the transmitter and receiver. Systematic system optimization techniques will be developed to power-optimally budget the slack in BER generated by the use of ECC across the most power-hungry blocks in the link. Prototype chip design is being planned to study the benefits of our design. These projects are funded by SRC, TI, and Intel.

Faculty collaborators: Elyse Rosenbaum, Andrew Singer, Jose Scutt-Aine